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| Automotive PWM DC/DC Voltage Controller ISL78210 The ISL78210 IC is a Single-Phase Synchronous-Buck PWM voltage controller featuring Intersil's Robust Ripple Regulator (R3TM) Technology. The ISL78210 provides a low cost solution for compact high performance applications.The wide 3.3V to 25V input voltage range is ideal for systems that run on battery or AC adapter power sources. Resistor programmed output voltage setpoint and capacitor programmed soft-start delay allow for fast and easy implementation. Robust integrated MOSFET drivers and Schottky bootstrap diode reduce the implementation area and lower component cost. Intersil's R3 TechnologyTM combines the best features of both fixed-frequency and hysteretic PWM control. The PWM frequency is 300kHz during static operation, becoming variable during changes in load, setpoint voltage, and input voltage when changing between battery and AC adapter power. The modulators ability to change the PWM switching frequency during these events in conjunction with external loop compensation produces superior transient response. For maximum efficiency, the converter automatically enters diode-emulation mode (DEM) during light-load conditions such as system standby. ISL78210 Features * Input Voltage Range: 3.3V to 25V * Output Voltage Range: 0.5V to 3.3V * Output Load to 30A * Simple Resistor Programming for Output Voltage * 0.75% System Accuracy: -40C to +105C * Capacitor Programming for Soft-Start Delay * Fixed 300kHz PWM Frequency in Continuous Conduction * External Compensation Affords Optimum Control Loop Tuning * Automatic Diode Emulation Mode for Highest Efficiency * Integrated High-Current MOSFET Drivers and Schottky Boot-Strap Diode for Optimal Efficiency * Choice of Overcurrent Detection Schemes - Lossless Inductor DCR Current Sensing - Precision Resistive Current Sensing * Power-Good Monitor for Soft-Start and Fault Detection * Fault Protection - Undervoltage - Overvoltage - Overcurrent (DCR-Sense or Resistive-Sense Capability) - Over-Temperature Protection - Fault Identification by PGOOD Pull-Down Resistance * TS16949 Compliant * Fully AEC-Q100 tested * Pb-Free (RoHS Compliant) Pin Configuration ISL78210 (16 LD 2.6X1.8 TQFN) TOP VIEW 16 PGND 15 LGATE 14 PVCC 13 VCC 12 BOOT 11 UGATE 10 PHASE 9 OCSET PGOOD 6 FB 7 VO 8 GND 1 EN 2 NC 3 SREF 4 NC 5 Applications*(see page 16) * Automotive PC Graphical Processing Unit VCC Rail * Automotive PC I/O Controller Hub (ICH) VCC Rail * Automotive PC Memory Controller Hub (GMCH) VCC Rail March 8, 2010 FN7583.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL78210 Pin Descriptions PIN 1 2 3, 5 4 6 SYMBOL GND EN NC SREF PGOOD DESCRIPTION IC ground for bias supply and signal reference. Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the soft-start sequence. No internal connection. Pins 3 and 5 should be connected to the GND pin. Soft-start programming capacitor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. The pull-down resistance between the PGOOD pin and the GND pin identifies which protective fault has shut down the regulator. See Table 1 on page 10. Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. The control loop compensation network connects between the FB pin and the converter output. See Figure 8 on page 11. Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. See Figure 5 on page 7. Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. See "OVERCURRENT PROGRAMMING CIRCUIT" on page 7. Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3 modulator. Inductor current polarity detector input. Connect to junction of output inductor, high-side MOSFET, and low-side MOSFET. See "Application Schematics" on page 4 (Figures 2 and 3). High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter. Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin. Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1F MLCC to the GND pin. See "Application Schematics" on page 4 (Figures 2 and 3). Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10F MLCC to the PGND pin. See "Application Schematics" on page 4 (Figures 2 and 3). Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter. Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET. 7 FB 8 9 VO OCSET 10 PHASE 11 12 UGATE BOOT 13 14 VCC PVCC 15 16 LGATE PGND Ordering Information PART NUMBER (Notes 2, 3) 1. ISL78210ARUZ-T (Note 1) GAT PART MARKING TEMP RANGE (C) -40 to +105 PACKAGE Tape & Reel (Pb-Free) 16 Ld 2.6x1.8 TQFN PKG. DWG. # L16.2.6x1.8A 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78210. For more information on MSL please see techbrief TB363. 2 FN7583.0 March 8, 2010 Block Diagram EN VCC 100k POR FB - EA + VCOMP FAULT 100pF H L IN RUN RUN PWM DRIVER BOOT UGATE PHASE PVCC 3 VW + - VSET SREF - OVP + FB - UVP + VREF GND 500mV FN7583.0 March 8, 2010 OTP PWM SHOOT-THROUGH PROTECTION RUN VCC gmVIN DRIVER LGATE PGND + - ISL78210 ISL78210 Cr VR + gmVO - - OCP + FAULT IOCSET 10F VO OCSET PGOOD FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL78210 ISL78210 Application Schematics RVCC +5V CPVCC LGATE PGND PVCC CVCC VIN 3.3V TO 25V VCC CINC BOOT UGATE PHASE ROCSET OCSET CBOOT QLS QHS LO VOUT 0.5V TO 3.3V COC COCSET COB CINB 16 15 14 7 FB GND EN GPIO NC SREF 1 2 3 4 5 6 PGOOD NC VO 8 13 12 11 10 9 RO RCOMP CCOMP CSOFT VCC RPGOOD ROFS RFB GPIO FIGURE 2. ISL78210 APPLICATION SCHEMATIC WITH DCR CURRENT SENSE RVCC +5V CPVCC LGATE PGND PVCC CVCC VIN 3.3V TO 25V VCC CINC BOOT UGATE PHASE OCSET CBOOT QLS QHS LO RSNS VOUT 0.5V TO 3.3V COC COCSET COB CINB 16 15 14 GND EN GPIO NC SREF 1 2 3 4 5 6 7 13 12 11 10 9 8 PGOOD NC FB VO ROCSET RO RCOMP CCOMP CSOFT VCC RPGOOD ROFS RFB GPIO FIGURE 3. ISL78210 APPLICATION SCHEMATIC WITH RESISTOR CURRENT SENSE 4 FN7583.0 March 8, 2010 ISL78210 Absolute Maximum Ratings VCC, PVCC, PGOOD to GND . . . . . . . . . . . . . -0.3V to +7.0V VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V GND to PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V EN, VO, FB, OCSET, SREF . . . . . . . -0.3V to GND, VCC +0.3V BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . -0.3V to 33V BOOT To PHASE Voltage (VBOOT-PHASE) . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V GND -8V (<20ns Pulse Width, 10J) UGATE Voltage . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V Charged Device Model . . . . . . . . . . . . . . . . . . . . . 2000V Latch Up (Tested per JESD-78A) Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) 16 Ld TQFN Package (Notes 4, 5) . 110 4.3 Junction Temperature Range . . . . . . . . . . -55C to +150C Operating Temperature Range . . . . . . . . . -40C to +105C Storage Temperature . . . . . . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . -40C to +105C Converter Input Voltage to GND . . . . . . . . . . . . 3.3V to 25V VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . 5V 5% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications These specifications apply for TA = -40C to +105C, unless otherwise stated. All typical specifications TA = +25C, VCC = 5V. Boldface limits apply over the operating temperature range, -40C to +105C. SYMBOL IVCC IVCCoff IPVCCoff VVCC_THR V VCC_THF PARAMETER VCC and PVCC VCC Input Bias Current VCC Shutdown Current PVCC Shutdown Current VCC POR THRESHOLD Rising VCC POR Threshold Voltage Falling VCC POR Threshold Voltage REGULATION Reference Voltage System Accuracy PWM Switching Frequency VO VO Input Voltage Range VO Input Impedance VO Reference Offset Current VO Input Leakage Current ERROR AMPLIFIER FB Input Bias Current SREF SREF Voltage Soft-Start Current TEST CONDITIONS EN = 5V, VCC = 5V, FB = 0.55V, SREF VREF(int) PWM Mode = CCM FSW VVO RVO IVOSS IVOoff IFB VSREF ISS EN = 5V VENTHR < EN, SREF = Soft-Start Mode EN = GND, VO = 3.6V EN = 5V, FB = 0.50V PWM Mode = CCM -0.75 270 0 -20 10 5 FN7583.0 March 8, 2010 ISL78210 Electrical Specifications These specifications apply for TA = -40C to +105C, unless otherwise stated. All typical specifications TA = +25C, VCC = 5V. Boldface limits apply over the operating temperature range, -40C to +105C. (Continued) SYMBOL RPG_SS RPG_UV RPG_OV RPG_OC PGOOD Leakage Current PGOOD Maximum Sink Current (Note 7) GATE DRIVER UGATE Pull-Up Resistance (Note 7) UGATE Source Current (Note 7) UGATE Sink Resistance (Note 7) UGATE Sink Current (Note 7) LGATE Pull-Up Resistance (Note 7) LGATE Source Current (Note 7) LGATE Sink Resistance (Note 7) LGATE Sink Current (Note 7) UGATE to LGATE Deadtime LGATE to UGATE Deadtime PHASE PHASE Input Impedance BOOTSTRAP DIODE Forward Voltage Reverse Leakage CONTROL INPUTS EN High Threshold Voltage EN Low Threshold Voltage EN Input Bias Current EN Leakage Current PROTECTION OCP Threshold Voltage OCP Reference Current OCSET Input Resistance OCSET Leakage Current UVP Threshold Voltage OVP Rising Threshold Voltage OVP Falling Threshold Voltage OTP Rising Threshold Temperature (Note 7) OTP Hysteresis (Note 7) NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. VOCPTH IOCP ROCSET IOCSET VUVTH VOVRTH VOVFTH TOTRTH TOTHYS VOCSET - VO EN = 5.0V EN = 5.0V EN = GND VFB = %VSREF VFB = %VSREF VFB = %VSREF -1.75 9.0 80 112 98 10 600 0 84 116 102 150 25 1.75 11 87 120 106 mV A k A % % % C C VENTHR VENTHF IEN IENoff EN = 5V EN = GND 2.0 1.4 2.0 0.1 1.0 2.5 1.0 V V A A VF IR PVCC = 5V, IF = 2mA VR = 25V 0.58 0.2 V A RPHASE 33 k RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR 200mA Source Current UGATE - PHASE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current LGATE - GND = 2.5V 250mA Sink Current LGATE - PGND = 2.5V UGATE falling to LGATE rising, no load LGATE falling to UGATE rising, no load 1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 21 21 1.5 1.5 1.5 0.9 A A A A ns ns IPG IPG_max TEST CONDITIONS PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5mA Sink PGOOD = 5V MIN MAX (Note 6) TYP (Note 6) UNIT 73 73 50 25 95 95 65 35 0.1 5.0 150 150 97 53 1.0 A mA PARAMETER POWER-GOOD PGOOD Pull-down Impedance 6 FN7583.0 March 8, 2010 ISL78210 Setpoint Reference Voltage The 500mV output of the setpoint reference voltage (VSREF) appears at the SREF pin. This signal is the output of the current limited voltage follower that buffers an internal 500mV voltage reference (VREF.) The converter is in regulation when the voltage at the FB pin (VFB) equals the VSREF voltage at the SREF pin. Both of these pins are measured relative to the GND pin, not the PGND pin. The feedback voltage-divider network consisting of offset resistor (ROFS) and loop-compensation resistor (RFB) scale down the converter output voltage (VOUT) such that the voltage VFB equals VSREF when VOUT equals the desired output voltage of the converter. The voltage-divider relation is given in Equation 1: R OFS V FB = V OUT --------------------------------R FB + R OFS (EQ. 1) discharge clamp, and enables the reference amplifier VSET. The soft-start current ISS is limited to 20A and is sourced out of the SREF pin and charges capacitor CSOFT until VSREF equals VREF. The regulator controls the PWM such that the voltage on the FB pin tracks the rising voltage on the SREF pin. The elapsed time from when the EN pin is asserted to when VSREF has charged CSOFT to VREF is called the soft-start delay tSS which is given by Equation 3: V SREF C SOFT t SS = -----------------------------------------I SS (EQ. 3) Where: - ISS is the soft-start current source at the 20A limit - VSREF is the buffered VREF reference voltage The end of soft-start is detected by ISS tapering off when capacitor CSOFT charges to VREF. The internal SSOK flag is set, the PGOOD pin goes high, and diode emulation mode (DEM) is enabled. Where: - VFB = VSREF - RFB is the loop-compensation feedback resistor that connects from the FB pin to the converter output - ROFS is the voltage-scaling programming resistor that connects from the FB pin to the GND pin The value of offset resistor ROFS must be recalculated whenever the value of loop-compensation resistor RFB has been changed. Calculation of ROFS is written as shown in Equation 2: V SREF R FB R OFS = ---------------------------------------V OUT - V SREF (EQ. 2) Component Selection For CSOFT Capacitor Choosing the CSOFT capacitor to meet the requirements of a particular soft-start delay tSS is calculated using Equation 4, which is written as follows: t SS I SS C SOFT = ---------------------V SREF (EQ. 4) Where: - tSS is the soft-start delay - ISS is the 20A soft-start current source at the 20A limit - VSREF is the buffered VREF reference voltage VOUT RFB ROFS Fault Protection FB - EA + VREF + VSET - VCOMP Overcurrent The overcurrent protection (OCP) setpoint is programmed with resistor ROCSET, which is connected across the OCSET and PHASE pins. Resistor RO is connected between the VO pin and the actual output voltage of the converter. During normal operation, the VO pin is a high impedance path, therefore there is no voltage drop across RO. The value of resistor RO should always match the value of resistor ROCSET. L DCR PHASE IL VDCR CSEN VO SREF CSOFT + ROCSET _ FIGURE 4. ISL78210 VOLTAGE PROGRAMMING CO Soft-Start Delay Circuit Description When the voltage on the VCC pin has ramped above the rising power-on reset voltage VVCC_THR, and the voltage on the EN pin has increased above the rising enable threshold voltage VENTHR, the SREF pin releases its 7 10A OCSET + VROCSET RO _ VO FIGURE 5. OVERCURRENT PROGRAMMING CIRCUIT FN7583.0 March 8, 2010 ISL78210 Figure 5 shows the overcurrent set circuit. The inductor consists of inductance L and the DC resistance DCR. The inductor DC current IL creates a voltage drop across DCR, which is given by Equation 5: V DCR = I L DCR (EQ. 5) The IOCSET current source sinks 10A into the OCSET pin, creating a DC voltage drop across the resistor ROCSET, which is given by Equation 6: V ROCSET = 10A R OCSET (EQ. 6) programmed to regulate 1.0V at the FB pin, that voltage would have to rise above the typical VOVRTH threshold of 116% for more than 2s in order to trip the OVP fault latch. In numerical terms, that would be 116% x 1.0V = 1.16V. When an OVP fault is declared, the PGOOD pin will pull-down to 65 and latch-off the converter. The OVP fault will remain latched until VCC has decayed below the falling POR threshold voltage V VCC_THF. An OVP fault cannot be reset by pulling the EN pin below the falling EN threshold voltage VENTHF. Although the converter has latched-off in response to an OVP fault, the LGATE gate-driver output will retain the ability to toggle the low-side MOSFET on and off, in response to the output voltage transversing the VOVRTH and VOVFTH thresholds. The LGATE gate-driver will turn-on the low-side MOSFET to discharge the output voltage, protecting the load. The LGATE gate-driver will turn-off the low-side MOSFET once the FB pin voltage is lower than the falling overvoltage threshold VOVRTH for more than 2s. The falling overvoltage threshold VOVFTH is typically 102%. That means if the FB pin voltage falls below 102% x 1.0V = 1.02V, for more than 2s, the LGATE gate-driver will turn off the low-side MOSFET. If the output voltage rises again, the LGATE driver will again turn on the low-side MOSFET when the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2s. By doing so, the IC protects the load when there is a consistent overvoltage condition. The DC voltage difference between the OCSET pin and the VO pin, which is given by Equation 7: V OCSET - V VO = V DCR - V ROCSET = I L DCR - I OCSET R OCSET (EQ. 7) The IC monitors the voltage of the OCSET pin and the VO pin. When the voltage of the OCSET pin is higher than the voltage of the VO pin for more than 10s, an OCP fault latches the converter off. Component Selection For ROCSET and CSEN The value of ROCSET is calculated with Equation 8 which is written as follows: I OC DCR R OCSET = --------------------------I OCSET (EQ. 8) Where: - ROCSET () is the resistor used to program the overcurrent setpoint - IOC is the output DC load current that will activate the OCP fault detection circuit - DCR is the inductor DC resistance For example, if IOC is 20A and DCR is 4.5m, the choice of ROCSET is = 20Ax4.5m/10A = 9k. Resistor ROCSET and capacitor CSEN form an R-C network to sense the inductor current. To sense the inductor current correctly not only in DC operation, but also during dynamic operation, the R-C network time constant ROCSET CSEN needs to match the inductor time constant L/DCR. The value of CSEN is then written as follows: L C SEN = ----------------------------------------R OCSET DCR (EQ. 9) Undervoltage The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold VUVTH for more than 2s. For example, if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to fall below the typical VUVTH threshold of 84% for more than 2s in order to trip the UVP fault latch. In numerical terms, that would be 84% x 1.0V = 0.84V. When a UVP fault is declared, the PGOOD pin will pull-down to 95 and latch-off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF. Over-Temperature When the temperature of the IC increases above the rising threshold temperature TOTRTH, it will enter the OTP state that suspends the PWM, forcing the LGATE and UGATE gate-driver outputs low. The status of the PGOOD pin does not change nor does the converter latch-off. The PWM remains suspended until the IC temperature falls below the hysteresis temperature TOTHYS, at which time normal PWM operation resumes. The OTP state can be reset if the EN pin is pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF. All other protection circuits remain functional while the IC is in the OTP state. It is likely that the IC will detect an UVP fault because in the absence of PWM, the output voltage decays below the undervoltage threshold VUVTH. For example, if L is 1.5H, DCR is 4.5m, and ROCSET is 9k, the choice of CSEN = 1.5H/(9kx4.5m) = 0.037F. When an OCP fault is declared, the PGOOD pin will pull-down to 35 and latch off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage V VCC_THF Overvoltage The OVP fault detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2s. For example, if the converter is 8 FN7583.0 March 8, 2010 ISL78210 The modulator features Intersil's R3 Robust-Ripple Regulator technology, a hybrid of fixed frequency PWM control and variable frequency hysteretic control. The PWM frequency is maintained at 300kHz under static continuous conduction mode operation within the entire specified envelope of input voltage, output voltage, and output load. If the application should experience a rising load transient and/or a falling line transient such that the output voltage starts to fall, the modulator will extend the on-time and/or reduce the off-time of the PWM pulse in progress. Conversely, if the application should experience a falling load transient and/or a rising line transient such that the output voltage starts to rise, the modulator will truncate the on-time and/or extend the off-time of the PWM pulse in progress. The period and duty cycle of the ensuing PWM pulses are optimized by the R3 modulator for the remainder of the transient and work in concert with the error amplifier VERR to maintain output voltage regulation. Once the transient has dissipated and the control loop has recovered, the PWM frequency returns to the nominal static 300kHz. Theory of Operation RIPPLE CAPACITOR VOLTAGE CR WINDOW VOLTAGE VW ERROR AMPLIFIER VOLTAGE VCOMP PWM FIGURE 6. MODULATOR WAVEFORMS DURING LOAD TRANSIENT Synchronous Rectification A standard DC/DC buck regulator uses a free-wheeling diode to maintain uninterrupted current conduction through the output inductor when the high-side MOSFET switches off for the balance of the PWM switching cycle. Low conversion efficiency as a result of the conduction loss of the diode makes this an unattractive option for all but the lowest current applications. Efficiency is dramatically improved when the free-wheeling diode is replaced with a MOSFET that is turned on whenever the high-side MOSFET is turned off. This modification to the standard DC/DC buck regulator is referred to as synchronous rectification, the topology implemented by the ISL78210 controller. Modulator The R3 modulator synthesizes an AC signal VR, which is an analog representation of the output inductor ripple current. The duty-cycle of VR is the result of charge and discharge current through a ripple capacitor CR. The current through CR is provided by a transconductance amplifier gm that measures the input voltage (VIN) at the PHASE pin and output voltage (VOUT) at the VO pin. The positive slope of VR can be written as Equation 10: V RPOS = ( g m ) ( V IN - V OUT ) C R (EQ. 10) The negative slope of VR can be written as Equation 11: V RNEG = g m V OUT C R (EQ. 11) Diode Emulation The polarity of the output inductor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. The DC component of the inductor current is positive, but the AC component known as the ripple current, can be either positive or negative. Should the sum of the AC and DC components of the inductor current remain positive for the entire switching period, the converter is in continuous-conduction-mode (CCM.) However, if the inductor current becomes negative or zero, the converter is in discontinuous-conduction-mode (DCM.) Unlike the standard DC/DC buck regulator, the synchronous rectifier can sink current from the output filter inductor during DCM, reducing the light-load efficiency with unnecessary conduction loss as the lowside MOSFET sinks the inductor current. The ISL78210 controller avoids the DCM conduction loss by making the low-side MOSFET emulate the current blocking behavior of a diode. This smart-diode operation called diode-emulation-mode (DEM) is triggered when the negative inductor current produces a positive voltage drop across the rDS(ON) of the low-side MOSFET for eight consecutive PWM cycles while the LGATE pin is high. The Where gm is the gain of the transconductance amplifier. A window voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating an envelope into which the ripple voltage VR is compared. The amplitude of VW is controlled internally by the IC. The VR, VCOMP, and VW signals feed into a window comparator in which VCOMP is the lower threshold voltage and VW is the higher threshold voltage. Figure 6 shows PWM pulses being generated as VR traverses the VW and VCOMP thresholds. The PWM switching frequency is proportional to the slew rates of the positive and negative slopes of VR; it is inversely proportional to the voltage between VW and VCOMP. 9 FN7583.0 March 8, 2010 ISL78210 converter will exit DEM on the next PWM pulse after detecting a negative voltage across the rDS(ON) of the low-side MOSFET. It is characteristic of the R3 architecture for the PWM switching frequency to decrease while in DCM, increasing efficiency by reducing unnecessary gate-driver switching losses. The extent of the frequency reduction is proportional to the reduction of load current. Upon entering DEM, the PWM frequency is forced to fall approximately 30% by forcing a similar increase of the window voltage V W. This measure is taken to prevent oscillating between modes at the boundary between CCM and DCM. The 30% increase of VW is removed upon exit of DEM, forcing the PWM switching frequency to jump back to the nominal CCM value. LGATE and UGATE MOSFET Gate-Drivers The LGATE pin and UGATE pins are MOSFET driver outputs. The LGATE pin drives the low-side MOSFET of the converter while the UGATE pin drives the high-side MOSFET of the converter. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET experiences long conduction times. In this environment, the low-side MOSFETs require exceptionally low rDS(ON) and tend to have large parasitic charges that conduct transient currents within the devices in response to high dv/dt switching present at the phase node. The drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the VGS(th) of the device can be exceeded and turned on. For this reason, the LGATE driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the MOSFETs gate voltage below VGS(th). Power-On Reset The IC is disabled until the voltage at the VCC pin has increased above the rising power-on reset (POR) threshold voltage VVCC_THR. The controller will become disabled when the voltage at the VCC pin decreases below the falling POR threshold voltage VVCC_THF. The POR detector has a noise filter of approximately 1s. Adaptive Shoot-Through Protection Adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 7 is extended by the additional period that the falling gate voltage remains above the 1V threshold. The high-side gate-driver output voltage is measured across the UGATE and PHASE pins while the low-side gate-driver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is supplied by a boot-strap capacitor connected across the BOOT and PHASE pins. The capacitor is charged each time the phase node voltage falls a diode drop below PVCC, such as when the low-side MOSFET is turned on. VIN and PVCC Voltage Sequence Prior to pulling EN above the VENTHR rising threshold voltage, the following criteria must be met: 1. VPVCC is at least equivalent to the VCC rising power-on reset voltage VVCC_THR 2. VVIN must be 3.3V or the minimum required by the application. Start-Up Timing Once VCC has ramped above VVCC_THR, the controller can be enabled by pulling the EN pin voltage above the input high threshold VENTHR. Approximately 20s later, the voltage at the SREF pin begins slewing to the designated VID set-point. The converter output voltage at the FB feedback pin follows the voltage at the SREF pin. During soft-start, the regulator always operates in CCM until the soft-start sequence is complete. PGOOD Monitor The PGOOD pin indicates when the converter is capable of supplying regulated voltage. The PGOOD pin is an undefined impedance if the VCC pin has not reached the rising POR threshold VVCC_THR, or if the VCC pin is below the falling POR threshold VVCC_THF. The PGOOD pull-down resistance corresponds to a specific protective fault, thereby reducing troubleshooting time and effort. Table 1 maps the pull-down resistance of the PGOOD pin to the corresponding fault status of the controller. TABLE 1. PGOOD PULL-DOWN RESISTANCE CONDITION VCC Below POR Soft-Start or Undervoltage Overvoltage Overcurrent PGOOD RESISTANCE Undefined 95 65 35 1V UGATE 1V 1V 1V LGATE FIGURE 7. GATE DRIVER ADAPTIVE SHOOT-THROUGH 10 FN7583.0 March 8, 2010 ISL78210 Compensation Design Figure 8 shows the recommended Type-II compensation circuit. The FB pin is the inverting input of the error amplifier. The COMP signal, the output of the error amplifier, is inside the chip and unavailable to users. CINT is a 100pF capacitor integrated inside the IC, connecting across the FB pin and the COMP signal. RFB, RCOMP, CCOMP and CINT form the Type-II compensator. The frequency domain transfer function is given by Equation 12: 1 + s ( R FB + R COMP ) C COMP G COMP ( s ) = -------------------------------------------------------------------------------------------------------------s R FB C INT ( 1 + s R COMP C ) COMP CINT = 100pF CCOMP A typical step-down DC/DC converter will have an IP-P of 20% to 40% of the maximum DC output load current. The value of IP-P is selected based upon several criteria, such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated using Equation 15: P COPPER = I LOAD DCR 2 (EQ. 15) Where ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance CO into which ripple current IP-P can flow. Current IP-P develops a corresponding ripple voltage VP-P across CO, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages are written as Equations 16 and 17: V ESR = I P - P E SR (EQ. 16) (EQ. 12) RCOMP EA COMP RFB FB ROFS VOUT + SREF and: FIGURE 8. COMPENSATION REFERENCE CIRCUIT The LC output filter has a double pole at its resonant frequency that causes rapid phase change. The R3 modulator used in the IC makes the LC output filter resemble a first order system in which the closed loop stability can be achieved with the recommended Type-II compensation network. Intersil provides a PC-based tool that can be used to calculate compensation network component values and help simulate the loop frequency response. IP - P V C = -------------------------------8 CO F SW (EQ. 17) General Application Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VP-P is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be considered. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IP-P is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases. Selection of the Input Capacitor The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. Figure 9 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as expressed in Equation 18: 2 2D 2 ( I MAX ( D - D ) ) + x I MAX ----- 12 I IN_RMS = ---------------------------------------------------------------------------------------------------I MAX Selecting the LC Output Filter The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is written as shown in Equation 13: VO D = --------V IN (EQ. 13) The output inductor peak-to-peak ripple current is written as shown in Equation 14: VO ( 1 - D ) I P - P = -----------------------------F SW L (EQ. 14) (EQ. 18) 11 FN7583.0 March 8, 2010 ISL78210 Where: - IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter Duty cycle is written as expressed in Equation 19: VO D = ------------------------V IN EFF (EQ. 19) 0.15F. A good quality ceramic capacitor such as X7R or X5R is recommended. 2.0 1.8 1.6 CBOOT_CAP (F) 1.4 1.2 1.0 0.8 0.6 nC 50 QGATE = 100nC In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET. NORMALIZED INPUT RMS RIPPLE CURRENT 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.1 0.2 0.3 0.4 x=1 x = 0.75 x = 0.50 x = 0.25 x=0 0.5 0.6 0.7 0.8 0.9 1.0 0.4 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VBOOT_CAP (V) 1.0 FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Driver Power Dissipation Switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125C. When designing the application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the drivers is approximated using Equation 21: P = Fsw ( 1.5V U Q + V L Q ) + P L + P U U L (EQ. 21) DUTY CYCLE FIGURE 9. NORMALIZED RMS INPUT CURRENT FOR x = 0.8 Selecting The Bootstrap Capacitor Adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. We selected the bootstrap capacitor breakdown voltage to be at least 10V. Although the theoretical maximum voltage of the capacitor is PVCC - VDIODE (voltage drop across the boot diode), large excursions below ground by the PHASE node requires that we select a capacitor with at least a breakdown rating of 10V. The bootstrap capacitor can be chosen from Equation 20: Q GATE C BOOT ----------------------V BOOT (EQ. 20) Where: Fsw is the switching frequency of the PWM signal VU is the upper gate driver bias supply voltage VL is the lower gate driver bias supply voltage QU is the charge to be delivered by the upper driver into the gate of the MOSFET and discrete capacitors - QL is the charge to be delivered by the lower driver into the gate of the MOSFET and discrete capacitors - PL is the quiescent power consumption of the lower driver - PU is the quiescent power consumption of the upper driver - Where: - QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET - VBOOT is the maximum decay across the BOOT capacitor As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is MOSFET Selection and Considerations Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. FN7583.0 March 8, 2010 12 ISL78210 1000 QU =100nC 900 QL =200nC 800 POWER (mW) 700 600 500 400 300 200 100 0 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k FREQUENCY (Hz) QU =20nC QL=50nC QU =50nC QL =100nC Layout Considerations QU =50nC QL=50nC The IC, analog signals, and logic signals should all be on the same side of the PCB, located away from powerful emission sources. The power conversion components should be arranged in a manner similar to the example in Figure 12 where the area enclosed by the current circulating through the input capacitors, high-side MOSFETs, and low-side MOSFETs is as small as possible and all located on the same side of the PCB. The power components can be located on either side of the PCB relative to the IC. GND GND OUTPUT OUTPUT CAPACITORS + + CAPACITORS FIGURE 11. POWER DISSIPATION vs FREQUENCY There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low switch charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET, which has the drain-source voltage clamped by its body diode during turn-off, the high-side MOSFET turns off with VIN -VOUT, plus the spike, across it. The preferred low-side MOSFET emphasizes low r DS(ON) when fully saturated to minimize conduction loss. For the low-side MOSFET, (LS), the power loss can be assumed to be conductive only and is written as Equation 22: P CON_LS I LOAD r DS ( ON )_LS ( 1 - D ) 2 VOUT VOUT PHASE PHASE NODE NODE LOW-SIDE LOW-SIDE MOSFETS MOSFETS INPUT INPUT CAPACITORS CAPACITORS HIGH-SIDE HIGH-SIDE MOSFETS MOSFETS VIN VIN FIGURE 12. TYPICAL POWER COMPONENT PLACEMENT Signal Ground The GND pin is the signal-common also known as analog ground of the IC. When laying out the PCB, it is very important that the connection of the GND pin to the bottom feedback voltage-divider resistor and the CSOFT capacitor be made as close as possible to the GND pin on a conductor not shared by any other components. In addition to the critical single point connection discussed in the previous paragraph, the ground plane layer of the PCB should have a single-point-connected island located under the area encompassing the IC, feedback voltage divider, compensation components, CSOFT capacitor, and the interconnecting traces among the components and the IC. The island should be connected using several filled vias to the rest of the ground plane layer at one point that is not in the path of either large static currents or high di/dt currents. The single connection point should also be where the VCC decoupling capacitor and the GND pin of the IC are connected. (EQ. 22) For the high-side MOSFET, (HS), its conduction loss is written as Equation 23: P CON_HS = I LOAD r DS ( ON )_HS D 2 (EQ. 23) For the high-side MOSFET, its switching loss is written as Equation 24: V IN I VALLEY t ON F V IN I PEAK t OFF F SW SW P SW_HS = --------------------------------------------------------------------- + ----------------------------------------------------------------2 2 (EQ. 24) Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off Power Ground Anywhere not within the analog-ground island is Power Ground. VCC AND PVCC PINS Place the decoupling capacitors as close as practical to the IC. In particular, the PVCC decoupling capacitor should have a very short and wide connection to the PGND pin. The VCC decoupling capacitor should not share any vias with the PVCC decoupling capacitor. EN AND PGOOD PINS These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. 13 FN7583.0 March 8, 2010 ISL78210 OCSET AND VO PINS The current-sensing network consisting of ROCSET, RO, and CSEN needs to be connected to the inductor pads for accurate measurement of the DCR voltage drop. These components however, should be located physically close to the OCSET and VO pins with traces leading back to the inductor. It is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. The procedure is the same for resistive current sense. FB AND SREF PINS The input impedance of these pins is high, making it critical to place the loop compensation components, feedback voltage divider resistors, and CSOFT capacitor close to the IC, keeping the length of the traces short. LGATE, PGND, UGATE, BOOT, AND PHASE PINS The signals going through these traces are high dv/dt and high di/dt, with high peak charging and discharging current. The PGND pin can only flow current from the gate-source charge of the low-side MOSFETs when LGATE goes low. Ideally, route the trace from the LGATE pin in parallel with the trace from the PGND pin; route the trace from the UGATE pin in parallel with the trace from the PHASE pin, and route the trace from the BOOT pin in parallel with the trace from the PHASE pin. These pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer. Copper Size for the Phase Node The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike. Typical Performance 100 95 90 EFFICIENCY (%) VIN = 12.6V REGULATION (%) 85 80 75 70 65 60 55 50 0 2 4 6 10 12 8 IOUT (A) 14 16 18 20 VIN = 8V 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 12 IOUT (A) 14 16 18 20 VIN = 12.6V VIN = 8V VIN = 19V VIN = 19V FIGURE 13. EFFICIENCY AT VOUT = 1.1V 1.0 0.8 REGULATION (%) 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 12 IOUT (A) 14 16 18 20 VIN = 8V VIN = 19V VIN = 12.6V FIGURE 14. LOAD REGULATION AT VOUT = 1.1V EN SREF VOUT PGOOD FIGURE 15. SWITCHING FREQUENCY AT VOUT = 1.1V FIGURE 16. START-UP, VIN = 12.6V, VOUT = 1.05V, LOAD = 10A 14 FN7583.0 March 8, 2010 ISL78210 Typical Performance (Continued) EN EN SREF SREF VOUT PGOOD PGOOD VOUT 20us FIGURE 17. START-UP INTO 750mV PRE-BIASED OUTPUT, VIN = 12.6V, VOUT = 1.05V, LOAD = 10A FIGURE 18. SHUT-DOWN, VIN = 12.6V, VOUT = 1.05V, LOAD = 50m EN VOUT PHASE SREF PGOOD VOUT UGATE LGATE 10s FIGURE 19. SHUT-DOWN, VIN = 12.6V, VOUT = 1.05V, LOAD = OPEN-CIRCUIT FIGURE 20. CCM STEADY-STATE OPERATION, VIN = 12.6V, VOUT = 1.0V, IOUT = 10A 15ADC VOUT +10A/A PHASE 5ADC VOUT IOUT -10A/A 5ADC UGATE PHASE LGATE FIGURE 21. DCM STEADY-STATE OPERATION, VIN = 12.6V, VOUT = 1.0V, IOUT = 3A FIGURE 22. CCM LOAD TRANSIENT RESPONSE VIN = 12.6V, VOUT = 1.0V 15 FN7583.0 March 8, 2010 ISL78210 Typical Performance (Continued) 11ADC +10A/A 1ADC IOUT VOUT -10A/A 1ADC PHASE FIGURE 23. DCM LOAD TRANSIENT RESPONSE VIN = 12.6V, VOUT = 1.0V Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 3/8/10 REVISION FN7583.0 Initial Release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78210 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7583.0 March 8, 2010 ISL78210 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D A B L16.2.6x1.8A 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA 2X 2X 0.10 C N E SYMBOL A MIN 0.45 - NOMINAL 0.50 0.127 REF MAX 0.55 0.05 NOTES - 12 0.10 C TOP VIEW A1 A3 b D 0.15 2.55 1.75 0.20 2.60 1.80 0.40 BSC 0.25 2.65 1.85 5 - 0.10 C 0.05 C SEATING PLANE A A1 SIDE VIEW C E e K L L1 0.15 0.35 0.45 0.40 0.50 16 4 4 0.45 0.55 2 3 3 e PIN #1 ID 12 L1 K NX L NX b 5 16X 0.10 M C A B 0.05 M C BOTTOM VIEW N Nd Ne NOTES: 0 - 12 4 Rev. 5 2/09 (DATUM B) (DATUM A) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.50 0.40 10 LAND PATTERN 0.20 17 FN7583.0 March 8, 2010 |
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